Integrated circuits require low resistance electricals contacts to conmponents, as well as low resistance interconnects or runners between components. Although polysilicon has a relatively low resistivity and has been widely and successfully used for both applications, alternative materials have been sought in an attempt to obtain even lower resistivites. As the dimensions of components continue to decrease, such lower resistivity alternatives become even more desirable because the resistance of the interconnect is inversely proportional to its cross-sectional area. At the present time, the most commonly used alternative to polysilicon is a transition metal silicide. Several techniques have been developed for fabricating such silicides. In one exemplary technique, fabrication of a silicide proceeds by depositing the transition metal, such as Ti or Co, on silicon and heating the resulting composite. The transitional metal reacts with the silicon to form the silicide. In one common embodiment of this technique, the silicon is present only where the silicide is ultimately desired and there is no need to remove unwanted silicide, although the unreacted metal must be removed by e.g., etching. The resulting silicide is self-aligned and is frequently referred to by those skilled in the art as salicide (self-aligned silicide). Salicides are used on gate electrodes, source/drain region electrical contacts, and interconnectss. Another exemplary technique fabricates structures that are called polycides. Polysilicon and transistion metal silicide layers are sequentially deposited and then simultaneously patterned. Both the gate and gate runner have a silicide on top. However, the gate etching may be difficult to control due to the silicide/polysilicon structure.
The chemical reaction between silicon and the metal necessarily consumes some of the underlying silicon; i.e., the underlying silicon reacts with the metal to form the silicide. However, deposition of a thick metal layer, necessary to obtain a thick, low-resistance, silicide layer, is frequently undesirable on both the gate and the source/drain regions. A thick silicide layer in the gate may produce either a high stress which adversely affects the quality of both the gate oxide and the device characteristics, or some silicide which penetrates the gate oxide and also adversely affect the device characteristics. The likelihood of the latter problem becomes greater as gate oxides continue to become thinner. Silicides are desirable on the source/drain regions because they have low resistance as compared to other materials. However, the source/drain regions should be shallow in integrated circuit devices having submicron features, and a thick metal deposition on these regions might lead to a reaction that would consume all, or a substantial fraction, of these regions.
Use of silicide containing structure for both the source/drain regions and the runners is theroretically possible, but is difficult to implement in practice because of the conflicting requirements of a thick silicide on the runners and a thin silicide on the source and drain regions. Generally, there exist similar considerations to the use of materials other than polysilicon and silicides in the gate and for interconnects.